Founding Engineer - FPGA / ASIC Engineer

<p><strong>At Zetta, we're building the next NVIDIA to accelerate AI discovery. Our XPU chips are state-of-the-art AI compute engines</strong>, versatile and efficient enough to support <strong><em>AGI</em></strong>, and eventually <strong><em>ASI</em></strong>, without requiring massive power infrastructure.</p> <p>We're a small founding team of engineers <strong>obsessed</strong> with pushing the boundaries of compute, and we're looking for the person who will <strong>own our chip design</strong>: from FPGA prototypes today to <strong>real silicon tapeouts</strong> tomorrow.</p> <h3><strong>You Are</strong></h3> <ul> <li><strong>Scrappy.</strong> You'd rather have a design running on hardware this week than a perfect spec next quarter</li> <li>Ready to go all-in and do the work of your life</li> <li>A technical powerhouse who loves living at the hardware-software boundary</li> <li>Hungry to own a chip <strong>end-to-end</strong>: architecture, RTL, verification, bring-up</li> <li>Deeply <strong>passionate</strong> and <strong>obsessed</strong> with computing and AI</li> <li>Someone who doesn't fret when faced with near-impossible technical challenges</li> </ul> <h3><strong>Your Background (important in bold)</strong></h3> <ul> <li>Background in Electrical Engineering, Computer Engineering, <em>or you taught yourself and can prove it</em></li> <li><strong>Strong digital design fundamentals</strong> (RTL, pipelining, clocking/reset strategy, latency vs. throughput tradeoffs, clean microarchitecture)</li> <li><strong>Hands-on FPGA experience</strong>: you've taken real designs from RTL to running on a board (Xilinx/AMD or Intel/Altera), debugged timing failures at 2am, and shipped something that worked</li> <li><strong>Synthesizable SystemVerilog/Verilog you're proud of</strong>: side projects, university work, open-source contributions, or professional experience all count</li> <li><strong>Toolchain fluency</strong>: simulation (Verilator, VCS/Xcelium/Questa, or open-source flows), linting, synthesis, timing constraints (SDC), and iterating toward timing closure</li> <li><strong>RTL quality instincts</strong> (assertions, CDC awareness, X-prop, code review hygiene, or the drive to build these habits fast)</li> <li><strong>Build/flow automation</strong> (Python, Tcl, bonus points for Nix or Makefile wizardry)</li> <li><strong>Comfort designing compute datapaths and memory subsystems</strong>: you understand bandwidth/latency-driven design even if you haven't shipped an AI accelerator yet</li> </ul> <h3><strong>Huge Plus If</strong></h3> <ul> <li><strong>Tapeout experience</strong>: university shuttle (Tiny Tapeout, MPW, Efabless), research chip, or professional. Any real silicon counts, and if you haven't taped out yet, this role is your path to it</li> <li><strong>FPGA prototyping of large designs</strong> (partitioning, multi-FPGA, emulation-style flows)</li> <li><strong>HW/SW bring-up experience</strong> (drivers/firmware, performance counters, profiling, debugging across the stack)</li> <li><strong>High-speed interface/IP integration</strong> (PCIe, DDR/HBM, Ethernet, SerDes)</li> <li><strong>Verification depth</strong> (UVM, formal, or cocotb-style Python testbenches)</li> <li><strong>Systems programming</strong> (Linux kernel modules, low-level software)</li> <li>Autodidactic polymath with a strong mathematical background</li> </ul> <h3><strong>What You'll Actually Do</strong></h3> <ul> <li><strong>Own the FPGA prototype</strong> of our XPU architecture: get it running, keep it running, make it fast</li> <li><strong>Write and review the RTL</strong> that becomes our first ASIC</li> <li><strong>Drive us to tapeout</strong> by building the design flow (lint, sim, synthesis, constraints) that gets us to real silicon</li> <li>Work across architecture, verification, and physical design to hit PPA targets</li> <li>Make critical architectural decisions that will live in silicon for years</li> </ul> <h3><strong>The Opportunity</strong></h3> <ul> <li><strong>Be one of the first employees shaping a revolutionary technology</s